1. Field of the Invention
The present invention relates generally to amplifiers and particularly to configurations of power amplifiers for multi-bands, such as dual bands or triple bands. More specifically, the present invention relates to configurations for preventing degradation of transistor characteristics of a multi-band power amplifier without deterioration of communication quality or increase in chip size.
2. Description of the Background Art
For power amplifiers for mobile communications, there are currently, commonly used a MMIC (monolithic microwave IC) or module (hybrid IC or multi-chip module) using a GaAs MESFET (metal-semiconductor filed effect transistor), a GaAs HEMT (high electron mobility transistor), or a GaAs HBT (hetero junction bipolar transistor). Of these transistors, a GaAs-HBT or a SiGe-HBT utilizing a hetero junction of gallium arsenide (GaAs) or of silicon germanium (SiGe) is currently most promising power devices for mobile communications, because they are more advantageous than a conventional field effect transistor (FET), in the following points:
(1) A negative gate bias voltage is not required and a single power supply operation can be achieved;
(2) Similarly to a Si-MOSFET (an insulated gate field effect transistor), no analog switch on the drain (or collector) side is required to perform an on/off operation to the output; and                (3) An output power density is very high and a prescribed output can be obtained with a power amplifier smaller in size than a FET power amplifier.        
A representative application of mobile communication is a mobile phone system. The mobile phone system includes the European Global System For Mobile Communications (GSM), a currently most widely used, 900 MHz-band mobile phone system, and the Digital Cordless Systems (DCS), a 1800 MHz-band mobile phone system widely used in Europe. In the GSM, DCS and other communication systems, a mobile phone of a high output of 1W to 4W is employed and a Si-MOSFET power amplifier, a main stream power amplifier for the mobile phone, is being replaced by a power amplifier making use of advantageous features of an HBT (an HBT power amplifier).
FIG. 14 schematically shows a configuration of a conventional GSM-DCS dual-band power amplification circuit. In FIG. 14, the dual-band power amplification circuit includes a DCS power amplifier 900 receiving a DCS signal IN_DCS and a bias voltage Vdcc to generate an output signal OUT_DCS when enabled, a GSM power amplifier 902 receiving an input signal IN_GSM and a bias voltage Vgcc and amplifying input signal IN_GSM to generate an output signal OUT_GSM when enabled, and a bias switch 904 for enabling one of DCS power amplifier 900 and GSM power amplifier 902 and also controlling a bias voltage of the enabled power amplifier in response to an output control voltage Vpc and a mode select signal Vmod.
Bias control voltage Vpc is generated for each of DCS power amplifier 900 and GSM power amplifier 902, individually.
In this dual-band power amplification circuit, one of DCS power amplifier 900 and GSM power amplifier 902 is enabled under the control of bias switch 904 in response to mode select signal Vmod. Either the output signal OUT_DCS output from DCS power amplifier 900 or the output signal OUT_GSM output from GSM power amplifier 902 is transmitted via a common antenna.
FIG. 15 shows an exemplary configuration of DCS power amplifier 900 shown in FIG. 14. In FIG. 15, DCS power amplifier 900 includes an input matching circuit 911 receiving input signal IN_DCS, a first amplification stage 912 amplifying a signal received through input matching circuit 911, a second amplification stage 914 receiving an output signal from the first amplification stage 912 via an inter-stage coupling circuit 913 to amplify the received signal, a third amplification stage 916 receiving a signal from the second amplification stage 914 via an inter-stage matching circuit 915 to amplify the received signal, and an output matching circuit 917 receiving an output signal from the third amplification stage 916 to generate the output signal OUT_DCS.
Input matching circuit 911 is constructed by a stub, a resistance and a capacitance element, and matches an input signal and an input impedance of power amplifier 900. Amplification stages 912, 914 and 916 receive collector bias voltages Vdc1, Vdc2 ad Vdc3, respectively. Amplification stages 912, 914 and 916 each include hetero-junction bipolar transistors (HBTs), as a power amplification element. Transistors Trd1 to Trd3 receive, at their respective collector nodes, collector bias voltages Vdc1, Vdc2 and Vdc3 via a stabilization circuit formed of a stub and a stabilizing capacitance element.
In amplification stages 912, 914 and 916, collector bias voltages Vdc1, Vdc2 and Vdc3 are applied to the respective collectors of power amplification transistors Trd1 Trd2 and Trd3 through the amplification circuit formed of the stub and the capacitance element, and to stably and quickly change the collector potentials of these transistors in accordance with the base potentials of the respective transistors.
DCS power amplifier 900 further includes a low pass filter 920 receiving DCS bias voltage Vdcc, bias voltage control circuits 921, 924 and 926 for adjusting the base voltages of power amplification transistors Trd1, Trd2 and Trd3 in accordance with bias voltage Vdcc from low pass filter 920 and a base bias control voltage VDCS from bias switch 904 shown in FIG. 14, and a mode switch circuit 922 responsive to mode select signal Vmodd received from bias switch 904 shown in FIG. 17 to selectively fix output bias voltages of bias voltage control circuits 921, 924 and 926 to a ground voltage level. Bias voltage control circuit 921 is formed of a resistance element.
Mode switch circuit 922 includes a switching transistor selectively rendered conductive in response to mode select signal Vmodd, and sets the power amplifier 900 in the in activated state or the in activated state in accordance with the on/off state of the switching transistor.
Mode select signal Vmodd is generated by bias switch 904 in response to mode select signal Vmod shown in FIG. 14. When mode select signal Vmodd is at an H (logical high) level, mode switch circuit 922 has the switching transistor turned on, to set the base voltages of power amplification transistors Trd1, Trd2 and Trd3 to a ground voltage level or a base to emitter voltage level to render power amplification transistors Trd1 to Trd3 non-conductive.
When mode select signal Vmodd is at an L (logical low) level, the switching transistor in mode switch circuit 922 is turned off and bias control voltage VDCS supplied from bias switch 904 is applied via bias voltage control circuit (a resistance element) 921 to the base of the first stage power amplification transistor Trd1. Power amplification transistors Trd2 and Trd3 receive, at their respective bases, bias voltages at a level according to bias voltage Vdcc and bias control voltage VDCS generated by bias voltage control circuits 924 and 926, respectively. In accordance with these base bias voltages, power amplification transistors Trd1, Trd2 and Trd3 each amplify a signal applied from a preceding matching circuit to the base thereof. Amplification stages 914 and 916 have the amplification rates adjusted in accordance with bias control voltage VDCS.
In FIG. 15, a block 930 surrounded by a broken line indicates a portion normally constructed by a single semiconductor chip, and outside the block 930, there are arranged the stub and the capacitance.
Final-stage power amplification transistor Trd3 generates output signal OUT_DCS via output matching circuit 917 and sends out the signal through a subsequent coupler to an antenna. Accordingly, final-stage power amplification transistor Trd3 has a driving capability made sufficiently larger than power amplification transistors Trd1 and Trd2 at the preceding stages. Final-stage power amplification transistor Trd3 has a collector node normally coupled to an externally arranged stub via a pad. An open stub is arranged at an output node and an output capacitance load is adjusted to stabilize a signal output from final-stage amplification stage 916.
FIG. 16 shows an exemplary configuration of GSM power amplifier 904 shown in FIG. 14. Referring to FIG. 16, GSM power amplifier 904 includes an input matching circuit 951 receiving GSM input signal IN_GSM, a first amplification stage 952 amplifying a signal received through input matching circuit 952, a second amplification stage 954 receiving a signal from the first-stage amplification stage 952 through an inter-stage matching circuit 953 to amplify the received signal, a third amplification stage 956 receiving a signal from the second amplification stage 954 through an inter-stage matching circuit 955 to amplify the received signal, and an output matching circuit 957 transmitting a signal received from the third amplification stage 956 to an output node.
The first, second and third amplification stages 952, 954 and 956 include power amplification transistors Trg1, Trg2 and Trg3, respectively. Power amplification transistor Trg1 receives, at a collector, a collector control voltage Vgc1 via a stabilization circuit formed of a stub and a capacitance element. Power amplification transistor Trg2 receives, at a collector, a collector control voltage Vgc2 via a stabilization circuit formed of a stub and a capacitance element. Power amplification transistor Trg3 receives, at a collector, a collector control voltage Vgc3 via a stabilization circuit formed of a capacitance element and a stub.
GSM power amplifier 904 further includes a low pass filter 960 receiving bias voltage Vgcc, a bias voltage control circuit (a resistance element) 961 for applying bias control voltage VGSM from bias switch 904 shown in FIG. 14 to the base of power amplification transistor Trg1, a bias voltage control circuit 964 adjusting a base bias voltage of power amplification transistor Trg2 in accordance with bias voltage Vgcc and bias control voltage VGSM, a bias control circuit 966 adjusting a base bias voltage of power amplification transistor Trg3 in accordance with bias voltage Vgcc and bias control voltage VGSM, and a mode switch circuit 962 responsive to a mode select signal Vmodg output from bias switch 904 shown in FIG. 14 to drive bias control voltage VGSM to a ground voltage level for setting power amplification transistors Trg1, Trg2 and Trg3 to a non-conductive state.
Mode switch circuit 962 includes a switching transistor selectively turning on in response to mode select signal Vmodg. Depending on whether the switching transistor is in an ON (conductive) state or an OFF (non-conductive) state, the GSM power amplifier is selectively set to an inactive state or an active state.
Mode select signal Vmodg is generated by the bias switch 904 shown in FIG. 14 in response to mode select signal Vmod. When mode select signal Vmodg is at H level, mode switch circuit 962 has its switching transistor turned on, bias control voltage VGSM attains an L level of a ground voltage level, and power amplification transistor Trg1 turns off. Furthermore, in bias control circuits 964 and 966, their respective output voltages attain the base-emitter voltage of power amplification transistors Trg2 and Trg3, and power amplification transistors Trg2 and Trg3 also turn off. Thus, in this state, GSM power amplifier 904 stops the power amplification operation.
When mode select signal Vmodg attains an L level, mode switch circuit 962 has its switching transistor turned off, power amplification transistors Trg1, Trg2, Trg3 have the base voltages biased by bias voltage control circuits 961, 964 and 966 in accordance with bias voltage VGSM and bias control voltage Vgcc, and amplify the signals received from their respective, preceding matching circuits.
The power amplifiers 900 and 904 shown in FIGS. 15 and 16 are only different in processing frequency and they have three amplification stages. Final-stage power amplification transistors Trd3 and Trg3 each have a sufficiently large current driving capability because each has its collector coupled to an output pad and drives an output load via output matching circuit 957 with a large driving power.
Bias switch 902 receives bias control voltages Vpcd and Vpcg respectively for the DCS and GSM modes, and also receives mode select signals Vmodd and Vmodg, and enables one of DCS and GSM power amplifiers 900 and 904 in response to the mode select signals.
Bias switch 902 selectively activates one of power amplifiers 900 and 904, so that communication is enabled in 1800 MHz-band DCS and 900 MHz-band GSM.
FIG. 17 schematically shows a configuration of a main portion of a mobile phone including the dual-band power amplification circuit. In FIG. 17, the mobile phone includes a battery power supply 980 supplying collector bias voltages Vdc1 to Vdc3 and bias voltage Vdcc for DCS power amplifier 900 and collector bias voltages Vgc1 to Vgc3 and bias voltage Vgcc for GSM power amplification circuit 902, a high frequency coupler 982 functioning as a band isolator transmitting a signal outputted from DCS power amplifier 900, a high frequency coupler 984 functioning as a band isolator transmitting a signal outputted from GSM power amplification circuit 902, a select circuit 986 responsive to a mode select signal (not shown) for selecting one of the signals output from high frequency couplers 982 and 984 to transmit the selected signal to an antenna 988, an output control circuit 990 monitoring a signal output from high frequency coupler 982, and generating bias control voltage Vpcd in accordance with the result of monitoring, and an output control circuit 992 monitoring a signal output from high frequency coupler 984 and generating bias control voltage Vpcg in accordance with the result of monitoring.
Output control circuits 990 and 992 apply bias control voltages Vpcd and Vpcg to bias switch 904 and in accordance with bias control voltages Vpcd and Vpcg, and bias switch 904 adjusts the levels of base bias voltages VDCS and VGSM to power amplification circuits 900 and 902.
For GSM and DCS applications, a power amplifier is required to deal with a high output power of no less than 1 W. Accordingly, in order to reduce power loss in a voltage regulator, bias voltages Vdc1 to Vdc3, Vdcc, Vgc1 to Vgc3 and Vgcc to power amplification circuits 900 and 902 are supplied directly from battery power supply 980.
DCS power amplification circuit 900 transmits the output signal, via high frequency coupler 982 and select circuit 985, to antenna 988. GSM power amplification circuit 902 transmits the output signal, via high frequency coupler 984 and select circuit, 986 to antenna 988. Between the output terminals of power amplification circuits 900 and 902 and an end of the antenna, normally there is not provided an isolator generally provided used in a domestic mobile phone (e.g., a personal digital cellular (PDC)) or others. This isolator is provided to prevent the variation of the output load impedance of power amplification circuits 900 and 902 when antenna terminal 988 varies in output impedance. In GSM and DCS applications, such an isolator is not used to achieve down-sizing and reduce output loss, and high frequency couplers 982 and 984 are simply used.
Thus, there is a severe condition of use for power amplifiers 900 and 902, such as a high power supply voltage condition upon completion of charging of battery power supply 980 and a variation in load of antenna terminal 988 directly exerted on power amplifiers 900 and 902. When an output load varies under the high power supply voltage condition, collector loss is increased to generate heat due to the current loss in the collector loss, and transistor cells constructing a power amplification transistor operate ununiformly. The power amplification transistor is caused because the power amplification transistor is constructed by a plurality of unit transistor cells and the operating temperature conditions for the unit cell transistors vary due to the distribution of the collector currents and the ununiform operation of the transistor cells is caused due to the variation in operation temperature condition.
In particular, the ununiform operation of unit cell transistors in final-stage power amplification transistor Trg3 or Trd3 would cause a current concentration that the operating currents of a part of unit cell transistors occupy a major portion of the whole operating current of the final-stage transistor. Consequently, variation in power output within a pulse in a burst operation is introduced and in the worst case, the final-stage power amplification transistor would be eventually destroyed.
Such current concentration due to generated heat is a disadvantage peculiar to a power amplifier having a plurality of unit transistor cells arranged closely adjacent to each other within a chip.
FIG. 18 schematically shows a layout of a chip of the power amplifiers shown in FIGS. 15 and 16. In FIG. 18, DCS and GSM power amplifiers 900 and 902 are formed in a semiconductor chip 999 at bi-divided regions, respectively. On this semiconductor chip, there are arranged the circuits indicated in FIGS. 15 and 16 by broken line blocks.
DCS power amplifier 900 has its first-stage power amplification transistor Trd1 arranged in a transistor formation region PWD1, and a second-stage power amplification transistor Trd2 arranged in a transistor formation region PWD2. Between transistor formation regions PWD2 and PWD1, a matching circuit arrangement region IMD12 is arranged, in which an inter-stage matching circuit 912 is formed to achieve an inter-stage matching between power amplifiers Trd1 and Trd2.
Furthermore, in DCS power amplifier 900 at a region IMD23, an inter-stage matching circuit 915 is arranged to achieve a matching between the second-stage power amplification transistors Trd2 and the third (final) stage power amplification transistor Trd3. Opposite to the transistor formation regions PWD1 and PWD2 and the matching circuit arrangement region IMD12 with respect to the matching circuit arrangement region IMN 23, a transistor formation region PWD3 for arranging the final-stage power amplification transistor Trd3 is arranged. The transistor formation region PWD1, the matching circuit arrangement region IMN12 and the transistor formation region PWD2 are aligned in a line, and adjacent to these regions the matching circuit arrangement region IMN23 is arranged adjacent to the regions PWD23, IMN12 and PWD2.
The first-stage power amplification transistor Trd1 is formed, for example, of two unit transistor cells. The second-stage power amplification transistor Trd2 is formed, for example, of ten unit transistor cells. The final-stage power amplification transistor Trd3 is formed, for example, of 6×10 unit transistor cells.
An empty region EPY is arranged adjacent to transistor formation region PWD3 for arranging the final-stage power amplification Trd3. Facing the empty region EPY and the transistor formation region PWD3, a pad region OBD is arranged in which bonding pads for output of DCS are arranged. Since the final-stage power amplification transistor Trd3 is made large in driving current and has an output signal line also made wide, a plurality of pads are arranged in pad region OBD to increase the output line width sufficiently.
For GSM power amplifier 902, the first-stage power amplification transistor Trg1 is arranged in a transistor formation region PWG1 and the second-stage power amplification transistor Trg2 is arranged in a transistor formation region PWG2. Between transistor formation regions PWG1 and PWG2, there is arranged a region IMG12 for arranging an inter-stage matching circuit 953. Regions PWG1, IMG12 and PWG2 are aligned on a line.
Adjacent to regions PWG1, PWG2 and IMG12, there is arranged a region IMG23 in which an inter-stage matching circuit 955 is laid out.
The final-stage power amplification transistor Trg3 is formed in a transistor formation region PWG3 adjacent to region IMG23 and arranged in alignment with the transistor formation region PWD3 and empty region EPY.
Power amplification transistor Trg1 is formed, for example, of four unit transistor cells, the second-stage power amplification transistor Trg2 is formed, for example, of 16 unit transistor cells, and the final-stage power amplification transistor Trg3 is formed, for example, of 10×10 unit transistor cells.
Adjacent to transistor formation region PWG3, an output bonding pad region OBG is provided in which output bonding pads for GSM are arranged.
Power amplifiers 900 and 902 are integrated on a semiconductor chip 999. As shown in FIG. 18, the regions for corresponding components of DCS power amplifiers 900 and 902 are arranged in parallel, power amplifiers 900 and 902, substantially identical in circuit configuration, are arranged efficiently and have the layout facilitated.
As shown in FIG. 18, in power amplifiers 900 and 902, their final-stage power amplification transistors are greater in current driving capability and occupy a larger chip area than the first- and second-stage power amplification transistors occupy.
FIG. 19 schematically shows a configuration of the final-stage power amplification transistors Trd3 and Trg3 of power amplifiers 900 and 902. The final-stage output amplification transistors Trd3 and Trg3 are merely different in the number of transistor cells included therein, and FIG. 19 shows a configuration of a single power amplification transistor.
In FIG. 19, the final-stage output amplification transistor includes unit transistors Tr11 to Tr1n through Trm1 to Trmn arranged in m rows and n columns, each of which are constructed by a hetero bipolar transistor (HBT).
Sub collector lines SL1 to SCLm are arranged corresponding to the rows of unit transistors, respectively, and sub base lines SBL1 to SBLm are arranged corresponding to the rows of unit transistor cells, respectively. Sub base lines SBL1-SBLm are coupled to a main base line MBL receiving a base bias voltage from a base bias voltage control circuit via a node A and a radio frequency (RF) input from a preceding inter-stage matching circuit via a node B. Sub collector lines SCL1-SCLm are commonly coupled to a main collector line MCL coupled to an output node C.
Unit transistors Tr11 to Tr1n through Trm1 to Trmn have their respective bases coupled to the corresponding sub base lines SBL1-SBLm through base ballast resistors Rb11 to Rb1n through Rbm1 to Rbmn. Furthermore, unit transistors Tr11 to Tr1n through Trm1 to Trmn have their respective emitters coupled to a ground node through emitter ballast resistors RE11 to Re1n through Rem1 to Remn, respectively.
When temperature rises and a collector current is increased, ballast resistors Rb11-Rb1n through Rbm1-Rbmn and Re11-Re1n through Rem1-Remn apply negative feedback to reduce base-emitter voltages of the corresponding unit transistors and prevent the collector currents from increasing. A bipolar transistor configured of the plurality of unit transistors is referred to as a multi-finger bipolar transistor.
FIG. 20 schematically shows a layout of the final-stage power amplification transistor shown in FIG. 19. In FIG. 20, unit cell regions 11-17, 21-27, 31-37, 41-47, 51-57, and 61-67, in each of which a unit transistor Tr is formed, are arranged in alignment in six rows. These unit cell regions are divided into three blocks BA, BB and BC each including unit cell regions aligned in two rows.
In each of unit cell regions 11-17, 21-27, 31-37, 41-47, 51-57, and 61-67, HBT is formed and an emitter region, a collector region and a base region are provided.
Sub emitter interconnection lines 5c1-5c6 are arranged each common to the unit cell regions aligned in a row (or unit transistor Tr), and are coupled to the emitter regions of unit cells on a corresponding row. Sub emitter interconnection lines 5c1-5c6 are connected to emitter interconnection lines 5a and 5b extending in the column direction on opposite sides of the unit transistor formation regions. Emitter interconnection lines 5a and 5b are coupled to a ground node supplying a ground voltage. In regions at which sub emitter interconnection lines 5c1-5c6 and unit transistors Tr formation region overlap with each other, emitter ballast resistors are formed, for example, of an epitaxial layer.
Base interconnection lines 2b1-2b3 are arranged in blocks BA-BC, respectively, common to the unit cell regions in the respective blocks. Sub base interconnection lines 2b1-2b3 are each arranged extending in a corresponding block through a region located between two rows of unit cell regions, and are each coupled to the base regions of the unit cells in the corresponding block via base ballast resistors 7.
Sub base interconnection lines 2b1-2b3 are coupled to a base interconnection line 2a coupled to an RF signal input portion 1 receiving a RF input from a preceding amplification stage through an inter-stage matching circuit. Base interconnection line 2a also receives a base bias control voltage from a corresponding bias voltage control circuit. Unit transistors Tr formed in unit cell regions 11-17 to 61-67 are each a heterojunction bipolar transistor HBT and sub base interconnection lines 2b1, 2b2 and 2b3 receive base currents Ib1, Ib2 and Ib3, respectively.
Furthermore, corresponding to each row of unit cell regions, sub collector interconnection lines 4b1-4b6 are provided each common to the unit cells in a corresponding row. Sub collector interconnection lines 4b1-4b6 are each coupled to the unit cells in a corresponding row at the collector regions in common. Sub collector interconnection lines 4b1-4b6 are commonly connected to a collector interconnection line 4a connected to an output portion 3 outputting a high frequency (RF) signal.
Sub collector interconnection lines 4b1-4b6 receive a current shunted from a collector current supplied to collector interconnection line 4a and thus receive collector currents Ic1-Ic6, respectively.
In an HBT, a collector current increases as temperature rises. If this temperature rise cannot be stopped, the collector current further increases and the increased current in tern further rises the temperature, and a current thus increases infinitely, or thermal run away is caused. To prevent this thermal run away, base ballast resistor 7 and an emitter ballast resistor (not shown) are arranged to prevent the collector current from increasing. In particular, connection of an emitter ballast resistor and base ballast resistor 7 to each unit transistor Tr prevents the ununiform or uneven distribution of collector current Ic caused by ununiformity in thermal distribution or the like of a multi-finger bipolar transistor formed of unit transistors Tr.
When such a transistor cell is arranged, sub collector interconnection lines 4b1-4b6 are adapted to be equal in line impedance for making collector currents Ic1-Ic6 flowing therethrough substantially uniform. In this case, as shown in FIG. 20 at a round region 8, in operation, a driving current causes a temperature distribution to cause such a temperature distribution in the transistor array that the center portion is high in temperature and the peripheral portion is low in temperature.
If such a temperature distribution is caused, there is a high possibility that a collector current concentrates in unit cell regions 34 and 44 at a center portion of the transistor array. If such a collector current concentration occurs, a major portion of the total of collector currents Ic1-Ic6 flows through unit transistors formed at unit cell regions 34 and 44 and the operating currents flowing through the unit cells in unit cell regions 34 and 44 thus occupies a major portion of the operating current of the final-stage power amplification transistor.
Thus, if a large collector current flows through unit cell regions 34 and 44, the following disadvantage would result; thermal runaway is caused in the round region 8, the transistors in unit cell regions 34 and 44 are destroyed a large current flows from collector interconnection line 4a to emitter interconnection lines 5a and 5b, and the entirety of the power amplification transistor is destroyed.
Such current concentration in a multi-finger bipolar transistor can effectively be avoided by increasing the spacing between unit transistors to suppress thermal interference between the unit transistors to arrange the unit transistors in a thermally isolated state from each other for reducing the overall thermal resistance. This, however, increases the layout area of the final-stage power amplification transistor and the increased area of the final-stage power amplification transistor, which occupies a large area of the chip, increases the chip size.
In particular, in a case of an HBT amplifier formed of a compound semiconductor such as GaAs, it is more expensive than a Si-MOSFET and reduction of chip area is important in view of price.
Japanese Patent Laying-Open No. 2001-102460 discloses such an arrangement that in a dual-band power amplification circuit, GSM and DCS power amplifiers do not operate simultaneously and the final-stage power amplification transistors of these GSM and DCS amplification circuits have their unit transistors arranged alternately. In this configuration, the transistor adjacent to a unit transistor does not operate. It is intended to alleviate the pitch condition on the unit transistors equivalently to reduce the thermal resistance to suppress heat generation.
However, GSM utilizes a frequency band of 900 MHz and DCS uses a frequency band of 1800 MHz. Therefore, in the configuration of arranging the unit transistors alternately, when GSM power amplifier is used, a harmonic thereof is transmitted to an output node of the DCS power amplifier through capacitive coupling of the final-stage power amplification transistors. Thus, as shown in FIG. 17, via coupler 982 and select circuit 986, a harmonic noise component provided from the DCS power amplifier is superimposed on this GSM transmission signal, and transmission quality would be deteriorated.
Furthermore, if the unit transistors of DCS and GSM output transistors are arranged in separate regions with a sufficient pitch condition in each region, and the separate regions for GSM and for DCS, similarly, due to a capacitive coupling between interconnection lines, a noise is superimposed and transmission quality is impaired. Furthermore, in this case, in view of reduction of chip area, the pitch of the unit transistors cannot sufficiently be increased, and the issue of the current concentration cannot sufficiently be overcome.